SN65LVDS348, 状态:ACTIVE
具有 -4 至 5V 共模范围的四路 LVDS 接收器
功能 样片 技术文档
质量和无铅数据 定价/封装 应用手册
相关产品 库存 模拟模型
工具与软件 符号/页脚 参考设计
数据表
Quad High-Speed Differential Receivers (sn65lvds348.pdf, 419 KB)
05 May 2004 下载(英文內容)
SN65LVDM31 SN65LVDS047 SN65LVDS048A SN65LVDS31 SN65LVDS32 SN65LVDS33 SN65LVDS348 SN65LVDS352 SN65LVDS390 SN65LVDS391
Supply Voltage(s)(V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
ICC(Max)(mA) 40 26 15 35 18 23 20 20 18 26
Operating Temp Range(Celsius) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85
Signaling Rate(Mbps) 150 400 400 400 400 400 340 560 630 630
No. of Tx 4 4 4 4
Tx tpd(Typ)(ns) 2.3 1.8 1.7 1.7
No. of Rx 4 4 4 4 4 4
Rx tpd(Typ)(ns) 2.4 2.1 4 6 6 2.5
Input Signal LVCMOS LVTTL LVDS LVTTL LVDS CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL LVDS LVTTL
Output Signal LVDM LVDS LVTTL LVDS LVTTL LVTTL LVTTL LVTTL LVTTL LVDS
Part-to-Part Skew(Max)(ps) 1000 1000 1000 800 1000 1000 1000 1500
ESD HBM(kV) 12 8 10 8 8 15 15 15 15 15
Approx. 1KU Price (US$) 1.55 1.30 1.30 1.50 1.50 1.60 1.60 1.80 1.50 1.50
Pin/Package 16SOIC 16SOIC,16TSSOP 16SOIC,16TSSOP 16SO,16SOIC,16TSSOP 16SO,16SOIC,16TSSOP 16SOIC,16TSSOP 16SOIC,16TSSOP 24TSSOP 16SOIC,16TSSOP 16SOIC,16TSSOP
样片 样片 样片 样片 样片 样片 样片 样片 样片 样片
库存 库存 库存 库存 库存 库存 库存 库存 库存 库存
产品信息
功能 将此信息保存至您的个人资料库
Meets or Exceeds the Requirements of ANSI TIA/EIA-644A Standard
Single-Channel Signaling Rates1 up to 560 Mbps
–4 V to 5 V Common-Mode Input Voltage Range
Flow-Through Architecture
Active Failsafe Assures a High-level Output When an Input Signal Is not Present
SN65LVDS348 Provides a Wide Common-Mode Range Replacement for the SN65LVDS048A or the DS90LV048A
APPLICATIONS
Logic Level Translator
Point-to-Point Baseband Data Transmission Over 100- Media
ECL/PECL-to-LVTTL Conversion
Wireless Base Stations
Central Office or PABX Switches
1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
说明
The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’352 adds two additional VCC and GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110- line termination resistor.
These receivers also provide 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range.
The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent-pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling.
The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space requirements and parts count by eliminating the need for a separate termination resistor. This can also improve signal integrity at the receiver by reducing the stub length from the line termination to the receiver.
The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from –40°C to 85°C.
缩小选择范围
- 选择指南
- 模拟混合信号: PECL PHY
支持
- 知识库
- 与技术支持联系
- TI 交叉参考
- 培训
- 查找部件标记(英文內容)
定价/封装/CAD 设计工具/样片
价格 封装 CAD 设计工具 样片
器件 状态 温度 (oC) 预算价格 ($US) | 数量 行业标准(TI 封装) | 引脚 顶端标记 标准封装数量 符号 尺寸 样片
SN65LVDS348D ACTIVE -40 to 85 1.60 | 1KU SOIC (D) | 16 查看 40 查看 查看 采购样片
SN65LVDS348DR ACTIVE -40 to 85 1.60 | 1KU SOIC (D) | 16 查看 2500 查看 查看 采购样片
SN65LVDS348DRG4 ACTIVE -40 to 85 1.60 | 1KU SOIC (D) | 16 查看 2500 查看 查看 采购样片
SN65LVDS348PW ACTIVE -40 to 85 1.60 | 1KU TSSOP (PW) | 16 查看 90 查看 查看 采购样片
SN65LVDS348PWG4 ACTIVE -40 to 85 1.60 | 1KU TSSOP (PW) | 16 查看 90 查看 查看 采购样片
SN65LVDS348PWR ACTIVE -40 to 85 1.60 | 1KU TSSOP (PW) | 16 查看 2000 查看 查看 采购样片
SN65LVDS348PWRG4 ACTIVE -40 to 85 1.60 | 1KU TSSOP (PW) | 16 查看 2000 查看 查看 采购样片
库存
TI 库存状态 已报告的分销商库存
SN65LVDS348D 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
6200* 1 Weeks 无报告
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SN65LVDS348DR 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
0* 8439 | 29 Mar 6 Weeks 无报告
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>10k | 3 May
SN65LVDS348DRG4 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
0* 8439 | 29 Mar 6 Weeks 无报告
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>10k | 3 May
SN65LVDS348PW 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
4850* 1 Weeks 无报告
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SN65LVDS348PWG4 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
4850* 1 Weeks 无报告
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SN65LVDS348PWR 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
0* >10k | 19 May 12 Weeks 无报告
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SN65LVDS348PWRG4 截至 8:02 PM GMT, 9 Mar 2006 截至 8:02 PM GMT, 9 Mar 2006
库存 在制数量 | 日期 交货周期 地区 公司 库存 采购
0* >10k | 19 May 12 Weeks 无报告
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质量与无铅数据
产品目录 DPPM / MTBF / FIT 率
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 详细信息 详细信息
SN65LVDS348D Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
SN65LVDS348DR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
SN65LVDS348DRG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
SN65LVDS348PW Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
SN65LVDS348PWG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
SN65LVDS348PWR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
SN65LVDS348PWRG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 查看 查看
计划的环保分级:无铅 (RoHS)、无铅(RoHS 豁免)或绿色环保(RoHS 和无 Sb/Br)- 请单击上表中产品目录明细的“查看”链接,以获得最新供货信息和附加产品目录明细。 如果此时没有在线提供您所请求的信息,则请联系 我们的产品信息中心, 以了解关于此信息可用性的信息。
技术文档
数据表 最新热点跟踪
Quad High-Speed Differential Receivers (sn65lvds348.pdf, 419 KB)
05 May 2004 下载(英文內容)
模拟模型
IBIS Model
SN65LVDS348 IBIS Model (sllc080.ibs, 31 KB)
29 Aug 2001 ibis(英文內容) / zip(英文內容)