七段译码器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY seven_v IS
PORT( D : IN INTEGER RANGE 0 TO 9;
S : OUT STD_LOGIC_VECTOR(0 DOWNTO 6) );
END seven_v ;
ARCHITECTURE a OF seven_v IS
BEGIN
PROCESS(D)
BEGIN
？？？
END PROCESS;
END a;
CASE D IS
WHEN 0 => S<="1111110"; --0
WHEN 1 => S<="0000110"; --1
WHEN 2 => S<="1101101"; --2
WHEN 3 => S<="1111001"; --3
WHEN 4 => S<="0110011"; --4
WHEN 5 => S<="1011011"; --5
WHEN 6 => S<="1011111"; --6
WHEN 7 => S<="1110000"; --7
WHEN 8 => S<="1111111"; --8
WHEN 9 => S<="1111011"; --9
WHEN OTHERS => S<="0000000";
END CASE;
半加器－（不考虑低位的进位）
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY hadd_v IS
PORT ( A, B : IN STD_LOGIC;
S, C : OUT STD_LOGIC);
END hadd_v;
ARCHITECTURE a OF hadd_v IS
SIGNAL temp : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
temp <= ('0'& A)+B;
S <= temp(0);
C <= temp(1);
END a;
全加器
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY fadd_v IS
PORT ( A, B, Ci : IN STD_LOGIC;
S, Co : OUT STD_LOGIC);
END fadd_v;
ARCHITECTURE a OF fadd_v IS
SIGNAL temp : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
temp <= ('0'& A)+B+Ci;
S <= temp(0);
Co <= temp(1);
END a;
四位加法器
全加器
全加器
全加器
半加器
进位
四位加法器－使用PACKAGE
library IEEE;
use IEEE.std_logic_1164.all;
package add_v is
COMPONENT hadd_v
PORT( a, b : IN STD_LOGIC;
s, c : OUTSTD_LOGIC);
END COMPONENT;
COMPONENT fadd_v
PORT( a, b, ci : IN STD_LOGIC;
s, co : OUT STD_LOGIC);
END COMPONENT;
end add_v;
四位加法器－使用PACKAGE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE Work.add_v.all;
ENTITY add4_v IS
PORT ( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout : OUTSTD_LOGIC );
END add4_v;
ARCHITECTURE a OF add4_v IS
Signal N1, N2, N3 : STD_LOGIC;
BEGIN
？？？
END a;
h0: hadd_v
PORT MAP (a =>A(0),b =>B(0),s =>S(0),c=>N1);
f1: fadd_v
PORT MAP (a =>A(1),b =>B(1),ci=>N1,s =>S(1),co=>N2);
f2: fadd_v
PORT MAP (a =>A(2),b =>B(2),ci=>N2,s =>S(2),co=>N3);
f3: fadd_v
PORT MAP (a =>A(3),b =>B(3),ci=>N3,s =>S(3),
co=>Cout);
四位加法器－元件例化
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY add4_v IS
PORT ( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout : OUT STD_LOGIC );
END add4_v;
ARCHITECTURE a OF add4_v IS
COMPONENT hadd_v
PORT( a, b : IN STD_LOGIC;
s, c : OUT STD_LOGIC);
END COMPONENT;
COMPONENT fadd_v
PORT( a, b, ci : IN STD_LOGIC;
s, co : OUT STD_LOGIC);
END COMPONENT;
Signal N1, N2, N3 : STD_LOGIC;
BEGIN
…
END a;
h0: hadd_v
PORT MAP (a =>A(0),b =>B(0),s =>S(0),c=>N1);
f1: fadd_v
PORT MAP (a =>A(1),b =>B(1),ci=>N1,s =>S(1),co=>N2);
f2: fadd_v
PORT MAP (a =>A(2),b =>B(2),ci=>N2,s =>S(2),co=>N3);
f3: fadd_v
PORT MAP (a =>A(3),b =>B(3),ci=>N3,s =>S(3),
co=>Cout);
D触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY dff_v is
PORT( CP,D : IN STD_LOGIC;
Q : OUT STD_LOGIC );
END dff_v;
ARCHITECTURE a OF dff_v IS
BEGIN
PROCESS (CP)
BEGIN
IF CP'event AND CP='1' THEN
Q <= D;
END IF;
END PROCESS;
END a;
每次时钟脉冲信号CP由0变1的上升沿，将输入信号D传
递至输出信号Q，而平时Q则保持过去的状态不变。这
就是一个寄存器。
RS触发器－真值表
未定 1 1
1 0 1
0 1 0
Qn-1 0 0
Q R S
RS触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rsff_v is
PORT( S,R : IN STD_LOGIC;
Q,NOT_Q : OUT STD_LOGIC);
END rsff_v;
ARCHITECTURE a OF rsff_v IS
SIGNAL QN,NOT_QN : STD_LOGIC;
BEGIN
QN <= R NOR NOT_QN;
NOT_QN <= S NOR QN;
Q <= QN;
NOT_Q <= NOT_QN;
END a;
只读存储器ROM(4x8)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY test is
PORT( DATAOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --Data Output
ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --ROM ADDRESS
CE : IN STD_LOGIC -- Chip Enable );
END test;
ARCHITECTURE a OF test IS
BEGIN…
END a;
DATAOUT <= "00001001" WHEN ADDR = "0000" AND CE='0' ELSE
"00011010" WHEN ADDR = "0001" AND CE='0' ELSE
"00011011" WHEN ADDR = "0010" AND CE='0' ELSE
"00101100" WHEN ADDR = "0011" AND CE='0' ELSE
"11100000" WHEN ADDR = "0100" AND CE='0' ELSE
"11110000" WHEN ADDR = "0101" AND CE='0' ELSE
"00010000" WHEN ADDR = "1001" AND CE='0' ELSE
"00010100" WHEN ADDR = "1010" AND CE='0' ELSE
"00011000" WHEN ADDR = "1011" AND CE='0' ELSE
"00100000" WHEN ADDR = "1100" AND CE='0' ELSE
"xxxxxxxx";
